Fan-Out Wafer Level Packaging processes are well-known within the semiconductor industry for producing microelectronic packages having peripheral fan-out areas, which enlarge the surface area of the package frontside over which a contact array can be formed. Fan-Out Wafer Level Packages (“FO-WLPs”) are commonly produced as System-in-Packages (“SiPs”) containing multiple microelectronic components, which are interconnected by redistribution layers formed over the molded package body. For example, a FO-WLP may be produced to include multiple Surface Mount Devices (“SMDs”) in addition to one or more semiconductor die. While enhancing the functionality of the package, the inclusion of multiple microelectronic components in a single package can require an increase in the number and/or wiring density of the redistribution layers. Such an increase in redistribution layer number and/or wiring density may increase package height and add undesired cost, complexity, and delay to the package fabrication process.
Additionally, higher redistribution layer counts and wiring densities can increase the likelihood of redistribution layer delamination during or after fabrication of the FO-WLP.
It is thus desirable to provide FO-WLPs and methods for fabricating FO-WLPs (or other microelectronic packages) containing multiple microelectronic components, which provide greater flexibility in the manner in which microelectronic components are interconnected. Ideally, embodiments of such FO-WLPs and package fabrication methods would enable a reduction in number, wiring density, or overall complexity of any redistribution layers included within the FO-WLPs. Other desirable features and characteristics of the present invention will become apparent from the subsequent Detailed Description and the appended Claims, taken in conjunction with the accompanying Drawings and the foregoing Background.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.